AI hardware hub awarded $16.3M from DOD

Three projects in the California-Pacific-Northwest AI Hardware Hub (NW-AI-Hub) aimed at dramatically improving the energy efficiency of artificial intelligence hardware are getting a $16.3 million boost from the Department of Defense.  

Co-led by Stanford University and UC Berkeley, the NW-AI-Hub is one of eight hubs funded in 2023 through the Microelectronics Commons program under the CHIPS and Science Act. The goal of the Microelectronics Commons initiative is to strengthen the nation’s semiconductor manufacturing capabilities and to reduce dependency on foreign sources of microelectronics.

“Energy efficiency of AI hardware is of paramount importance because the energy consumption of AI is a key bottleneck for its ubiquitous deployment in society,” said H.-S. Philip Wong, chair of the hub’s executive committee and professor of electrical engineering at Stanford University. “The California and Pacific Northwest region is delighted to have the opportunity to contribute to lab-to-fab translation of advanced AI hardware technologies that are essential to ensure the national security and economic development of this country.”

The federal awards, which cover the first year of research, are among $269 million in Microelectronics Commons project awards announced by the Department of Defense. 

Tsu-Jae King Liu, dean of UC Berkeley’s College of Engineering and executive committee co-chair of the NW-AI-Hub, said this investment in microelectronics research will ensure continued innovations in the field of AI. 

“Our hub brings together dozens of academic institutions, National Labs and industry partners to develop innovations with impact throughout the entire semiconductor value chain,” said Liu. “This includes materials, devices, electronic design automation and chip design, and packaging, as well as system prototyping and testing.”

The three funded projects from the NW-AI-Hub are:

• CMOS+X: Integrated Ferroelectric Technologies for Ultra Efficient AI Hardware, led by Sayeef Salahuddin, UC Berkeley professor of electrical engineering and computer sciences. This project aims to substantially improve energy efficiency for future AI hardware by exploiting unique properties of ferroelectric materials. Research will focus on lowering the power supply voltage of computing hardware as well as achieving non-volatile memory that can be directly integrated with the microprocessor. 
• Energy-Efficient and Scalable AI Hardware Systems through Heterogeneous Integration of Specialized Chiplets, led by Subhasish Mitra, professor of electrical engineering and computer science at Stanford. This project will use innovations in semiconductor materials, integration technologies and AI system architecture to drastically improve energy consumption and performance of AI hardware.  Forming the foundation for such AI systems are interconnected heterogeneous chiplets, built using leading-edge CMOS and 3D CMOS+X semiconductor technologies, such as carbon nanotube transistors, resistive memory and oxide semiconductors. 
• Energy-Efficient and Scalable, and Self-learning AI Hardware with 3D Electronic-Photonic-Integrated-Circuits, led by S.J. Ben Yoo, UC Davis professor of electrical and computer engineering. This project pursues transformative improvements in AI Hardware’s speed, energy-efficiency, scalability, and self-learning capabilities for next-generation U.S. defense needs.  The project approach combines “best-of-both-worlds” innovations in photonics and electronics including CMOS+X devices and integrates them into compact 3D photonic-electronic-integrated circuit modules.

The three projects include more than 20 hub partners from academia, industry and government laboratories.